1. Field of the Invention
The present invention relates to a method for fabricating a crown capacitor, and more particularly to a method for fabricating a crown capacitor with a rough surface.
2. Description of the Related Art
Recently, capacitors have become more important in semiconductor circuit design; it is a circuit device that can't be substituted. For example, the device is widely used in dynamic random access memory (DRAM), oscillators, time delay circuitry, an analog/digital (A/D) converters, digital/analog (D/A) converters, and many other application circuits.
A capacitor is basically composed an insulating material disposed between two conducting layers. The ability of a capacitor to store charge is related to three physical characteristics: (1) the width of the insulating material; (2) the surface of the plates; and (3) the electric and/or mechanical characteristics of the insulating material and the plates.
Take a DRAM for example. In order to better integrate memory, a large number of memory cells must be fit in a memory circuit; thus, the base area of a memory cell must be minimized. Also, the plates of a memory cell must have sufficient surface area to store enough charge.
According to the reasons described above, a three-dimensioned stacked capacitor cell (STC) has been developed for a compact memory device. The space in the wafer under the device is used so that the surface areas of the plates of the capacitor are increased. The advantages of this structure are the low soft error rate (SER), and the fact that it can be combined with an insulating layer with high dielectric constant.
In order to increase the capacitance of a DRAM memory cell capacitor, it has been determined to be advantageous to form a rough surface on the storage-node capacitor plates. Referring to FIG. 1, the process begins with thermal oxidation of P-substrate 100, such as local oxidation (LOCOS) to form a field insulator 101 to insulate an active area. Then semiconductor processes like deposition, photolithography, and ion implantation are applied to form a wordline 141 connecting to another memory cell and to form a semiconductor device, for example a transistor 143 composed of a gate 141' and diffusion regions including a source region and a drain region. The wordline 141 and the gate 141' are formed of polycrystalline silicon.
Next, a boro-phospho-silicate-glass (BPSG) layer 148 is formed to isolate the transistors and a conducting layer is formed thereafter. The BPSG layer 148 is defined by the processes of photolithography and etching to form an opening to be, for example, a source or a drain contact hole. Then a polycrystalline silicon layer (not shown) is formed upon the BPSG layer 148 and is filled in the source or the drain contact hole so that a plug 147 electrically contacting the source region 145 is formed. Then the polycrystalline silicon plates 210 are etched back to form a storage-node capacitor. Then a hemispherical-grain (HSG) polycrystalline silicon is selectively grown on the surface of the plates. Then a dielectric layer 230 is conformably formed on the storage-node capacitor plates 210 with HSG polycrystalline silicon. An upper plate 250 is then formed on the dielectric layer 230 and the fabrication of a capacitor of a DRAM cell is completed.
As described above, the growth of HSG polycrystalline silicon must be selective to prevent the storage-node capacitor plates from short-circuiting with each other. Furthermore, the residual impurity on the storage-node capacitor plates will cause the phenomenon of the discontinuous growth of the HSG polycrystalline silicon. Further, it is difficult to fill the dielectric layer into the space 270 because the HSG polycrystalline silicon on the side-walls of the storage-node capacitor plates 210 fills in and decreases the size of the space 270.